diff --git a/src/ergogen.js b/src/ergogen.js index 33234c5..1fd0351 100644 --- a/src/ergogen.js +++ b/src/ergogen.js @@ -80,7 +80,7 @@ const process = async (raw, debug=false, logger=()=>{}) => { } logger('Scaffolding PCBs...') - const pcbs = pcbs_lib.parse(config.pcbs || {}, points, outlines, units) + const pcbs = pcbs_lib.parse(config, points, outlines, units) results.pcbs = {} for (const [pcb_name, pcb_text] of Object.entries(pcbs)) { if (!debug && pcb_name.startsWith('_')) continue diff --git a/src/pcbs.js b/src/pcbs.js index 1377a77..0fbf309 100644 --- a/src/pcbs.js +++ b/src/pcbs.js @@ -234,7 +234,7 @@ const footprint = exports._footprint = (config, name, points, point, net_indexer exports.parse = (config, points, outlines, units) => { - const pcbs = a.sane(config || {}, 'pcbs', 'object')() + const pcbs = a.sane(config.pcbs || {}, 'pcbs', 'object')() const results = {} for (const [pcb_name, pcb_config] of Object.entries(pcbs)) { @@ -301,8 +301,12 @@ exports.parse = (config, points, outlines, units) => { const nets_text = nets_arr.join('\n') const footprint_text = footprints.join('\n') const outline_text = Object.values(kicad_outlines).join('\n') + const personalized_prefix = kicad_prefix + .replace('KEYBOARD_NAME_HERE', pcb_name) + .replace('VERSION_HERE', config.meta && config.meta.version || 'v1.0.0') + .replace('YOUR_NAME_HERE', config.meta && config.meta.author || 'Unknown') results[pcb_name] = ` - ${kicad_prefix} + ${personalized_prefix} ${nets_text} ${netclass} ${footprint_text} diff --git a/test/cli/big/reference/pcbs/_export.kicad_pcb b/test/cli/big/reference/pcbs/_export.kicad_pcb index 3e5ec29..8644559 100644 --- a/test/cli/big/reference/pcbs/_export.kicad_pcb +++ b/test/cli/big/reference/pcbs/_export.kicad_pcb @@ -4,9 +4,9 @@ (page A3) (title_block - (title KEYBOARD_NAME_HERE) - (rev VERSION_HERE) - (company YOUR_NAME_HERE) + (title _export) + (rev v1.0.0) + (company Unknown) ) (general diff --git a/test/cli/big/reference/pcbs/export.kicad_pcb b/test/cli/big/reference/pcbs/export.kicad_pcb index 3e5ec29..d2e5a7b 100644 --- a/test/cli/big/reference/pcbs/export.kicad_pcb +++ b/test/cli/big/reference/pcbs/export.kicad_pcb @@ -4,9 +4,9 @@ (page A3) (title_block - (title KEYBOARD_NAME_HERE) - (rev VERSION_HERE) - (company YOUR_NAME_HERE) + (title export) + (rev v1.0.0) + (company Unknown) ) (general diff --git a/test/cli/medium/reference/pcbs/export.kicad_pcb b/test/cli/medium/reference/pcbs/export.kicad_pcb index 3e5ec29..d2e5a7b 100644 --- a/test/cli/medium/reference/pcbs/export.kicad_pcb +++ b/test/cli/medium/reference/pcbs/export.kicad_pcb @@ -4,9 +4,9 @@ (page A3) (title_block - (title KEYBOARD_NAME_HERE) - (rev VERSION_HERE) - (company YOUR_NAME_HERE) + (title export) + (rev v1.0.0) + (company Unknown) ) (general diff --git a/test/pcbs/001_mock_footprints___pcbs.json b/test/pcbs/001_mock_footprints___pcbs.json index fda7b7d..c4083c7 100644 --- a/test/pcbs/001_mock_footprints___pcbs.json +++ b/test/pcbs/001_mock_footprints___pcbs.json @@ -1,3 +1,3 @@ { - "main": "\n \n(kicad_pcb (version 20171130) (host pcbnew 5.1.6)\n\n (page A3)\n (title_block\n (title KEYBOARD_NAME_HERE)\n (rev VERSION_HERE)\n (company YOUR_NAME_HERE)\n )\n\n (general\n (thickness 1.6)\n )\n\n (layers\n (0 F.Cu signal)\n (31 B.Cu signal)\n (32 B.Adhes user)\n (33 F.Adhes user)\n (34 B.Paste user)\n (35 F.Paste user)\n (36 B.SilkS user)\n (37 F.SilkS user)\n (38 B.Mask user)\n (39 F.Mask user)\n (40 Dwgs.User user)\n (41 Cmts.User user)\n (42 Eco1.User user)\n (43 Eco2.User user)\n (44 Edge.Cuts user)\n (45 Margin user)\n (46 B.CrtYd user)\n (47 F.CrtYd user)\n (48 B.Fab user)\n (49 F.Fab user)\n )\n\n (setup\n (last_trace_width 0.25)\n (trace_clearance 0.2)\n (zone_clearance 0.508)\n (zone_45_only no)\n (trace_min 0.2)\n (via_size 0.8)\n (via_drill 0.4)\n (via_min_size 0.4)\n (via_min_drill 0.3)\n (uvia_size 0.3)\n (uvia_drill 0.1)\n (uvias_allowed no)\n (uvia_min_size 0.2)\n (uvia_min_drill 0.1)\n (edge_width 0.05)\n (segment_width 0.2)\n (pcb_text_width 0.3)\n (pcb_text_size 1.5 1.5)\n (mod_edge_width 0.12)\n (mod_text_size 1 1)\n (mod_text_width 0.15)\n (pad_size 1.524 1.524)\n (pad_drill 0.762)\n (pad_to_mask_clearance 0.05)\n (aux_axis_origin 0 0)\n (visible_elements FFFFFF7F)\n (pcbplotparams\n (layerselection 0x010fc_ffffffff)\n (usegerberextensions false)\n (usegerberattributes true)\n (usegerberadvancedattributes true)\n (creategerberjobfile true)\n (excludeedgelayer true)\n (linewidth 0.100000)\n (plotframeref false)\n (viasonmask false)\n (mode 1)\n (useauxorigin false)\n (hpglpennumber 1)\n (hpglpenspeed 20)\n (hpglpendiameter 15.000000)\n (psnegative false)\n (psa4output false)\n (plotreference true)\n (plotvalue true)\n (plotinvisibletext false)\n (padsonsilk false)\n (subtractmaskfromsilk false)\n (outputformat 1)\n (mirror false)\n (drillshape 1)\n (scaleselection 1)\n (outputdirectory \"\"))\n )\n\n (net 0 \"\")\n(net 1 \"P1\")\n(net 2 \"T3_1\")\n(net 3 \"T3_2\")\n(net 4 \"T3_3\")\n \n (net_class Default \"This is the default net class.\"\n (clearance 0.2)\n (trace_width 0.25)\n (via_dia 0.8)\n (via_drill 0.4)\n (uvia_dia 0.3)\n (uvia_drill 0.1)\n (add_net \"\")\n(add_net \"P1\")\n(add_net \"T3_1\")\n(add_net \"T3_2\")\n(add_net \"T3_3\")\n )\n\n \n\n (module trace_test (layer F.Cu) (tedit 5CF31DEF)\n\n (at 1 -1 30)\n\n (pad 1 smd rect (at 0 0 30) (size 1 1) (layers F.Cu F.Paste F.Mask)\n (net 1 \"P1\") (solder_mask_margin 0.2))\n\n (pad 2 smd rect (at 5 5 30) (size 1 1) (layers F.Cu F.Paste F.Mask)\n (net 1 \"P1\") (solder_mask_margin 0.2))\n\n )\n\n (segment (start 1 -1) (end 7.830127 0.8301270000000001) (width 0.25) (layer F.Cu) (net 1))\n\n \n\n\n (module zone_test (layer F.Cu) (tedit 5CF31DEF)\n\n (at 1 -1 30)\n\n (pad 1 smd rect (at 0 0 30) (size 1 1) (layers F.Cu F.Paste F.Mask)\n (net 1 \"P1\") (solder_mask_margin 0.2))\n\n (pad 2 smd rect (at 5 5 30) (size 1 1) (layers F.Cu F.Paste F.Mask)\n (net 1 \"P1\") (solder_mask_margin 0.2))\n\n )\n\n (zone (net 1) (net_name P1) (layer F.Cu) (tstamp 0) (hatch full 0.508)\n (connect_pads (clearance 0.508))\n (min_thickness 0.254)\n (fill yes (arc_segments 32) (thermal_gap 0.508) (thermal_bridge_width 0.508))\n (polygon (pts (xy 7.830127 0.8301270000000001) (xy 2.830127 -7.830127) (xy -5.830127 -2.830127) (xy -0.8301270000000001 5.830127)))\n )\n\n \n \n\n (module dynamic_net_test (layer F.Cu) (tedit 5CF31DEF)\n\n (at 0 0 0)\n\n (pad 1 smd rect (at 0 0 0) (size 1 1) (layers F.Cu F.Paste F.Mask)\n (net 2 \"T3_1\") (solder_mask_margin 0.2))\n\n (pad 1 smd rect (at 0 0 0) (size 1 1) (layers F.Cu F.Paste F.Mask)\n (net 3 \"T3_2\") (solder_mask_margin 0.2))\n\n (pad 1 smd rect (at 0 0 0) (size 1 1) (layers F.Cu F.Paste F.Mask)\n (net 4 \"T3_3\") (solder_mask_margin 0.2))\n\n )\n\n \n \n\n (module anchor_test (layer F.Cu) (tedit 5CF31DEF)\n\n (at 0 0 0)\n\n (fp_line (start 0 0) (end 10 -10) (layer Dwgs.User) (width 0.05))\n\n )\n\n \n (gr_line (start -9.5 9.5) (end 9.5 9.5) (angle 90) (layer Edge.Cuts) (width 0.15))\n(gr_line (start 9.5 9.5) (end 9.5 -9.5) (angle 90) (layer Edge.Cuts) (width 0.15))\n(gr_line (start 9.5 -9.5) (end -9.5 -9.5) (angle 90) (layer Edge.Cuts) (width 0.15))\n(gr_line (start -9.5 -9.5) (end -9.5 9.5) (angle 90) (layer Edge.Cuts) (width 0.15))\n \n)\n\n " + "main": "\n \n(kicad_pcb (version 20171130) (host pcbnew 5.1.6)\n\n (page A3)\n (title_block\n (title main)\n (rev v1.0.0)\n (company Unknown)\n )\n\n (general\n (thickness 1.6)\n )\n\n (layers\n (0 F.Cu signal)\n (31 B.Cu signal)\n (32 B.Adhes user)\n (33 F.Adhes user)\n (34 B.Paste user)\n (35 F.Paste user)\n (36 B.SilkS user)\n (37 F.SilkS user)\n (38 B.Mask user)\n (39 F.Mask user)\n (40 Dwgs.User user)\n (41 Cmts.User user)\n (42 Eco1.User user)\n (43 Eco2.User user)\n (44 Edge.Cuts user)\n (45 Margin user)\n (46 B.CrtYd user)\n (47 F.CrtYd user)\n (48 B.Fab user)\n (49 F.Fab user)\n )\n\n (setup\n (last_trace_width 0.25)\n (trace_clearance 0.2)\n (zone_clearance 0.508)\n (zone_45_only no)\n (trace_min 0.2)\n (via_size 0.8)\n (via_drill 0.4)\n (via_min_size 0.4)\n (via_min_drill 0.3)\n (uvia_size 0.3)\n (uvia_drill 0.1)\n (uvias_allowed no)\n (uvia_min_size 0.2)\n (uvia_min_drill 0.1)\n (edge_width 0.05)\n (segment_width 0.2)\n (pcb_text_width 0.3)\n (pcb_text_size 1.5 1.5)\n (mod_edge_width 0.12)\n (mod_text_size 1 1)\n (mod_text_width 0.15)\n (pad_size 1.524 1.524)\n (pad_drill 0.762)\n (pad_to_mask_clearance 0.05)\n (aux_axis_origin 0 0)\n (visible_elements FFFFFF7F)\n (pcbplotparams\n (layerselection 0x010fc_ffffffff)\n (usegerberextensions false)\n (usegerberattributes true)\n (usegerberadvancedattributes true)\n (creategerberjobfile true)\n (excludeedgelayer true)\n (linewidth 0.100000)\n (plotframeref false)\n (viasonmask false)\n (mode 1)\n (useauxorigin false)\n (hpglpennumber 1)\n (hpglpenspeed 20)\n (hpglpendiameter 15.000000)\n (psnegative false)\n (psa4output false)\n (plotreference true)\n (plotvalue true)\n (plotinvisibletext false)\n (padsonsilk false)\n (subtractmaskfromsilk false)\n (outputformat 1)\n (mirror false)\n (drillshape 1)\n (scaleselection 1)\n (outputdirectory \"\"))\n )\n\n (net 0 \"\")\n(net 1 \"P1\")\n(net 2 \"T3_1\")\n(net 3 \"T3_2\")\n(net 4 \"T3_3\")\n \n (net_class Default \"This is the default net class.\"\n (clearance 0.2)\n (trace_width 0.25)\n (via_dia 0.8)\n (via_drill 0.4)\n (uvia_dia 0.3)\n (uvia_drill 0.1)\n (add_net \"\")\n(add_net \"P1\")\n(add_net \"T3_1\")\n(add_net \"T3_2\")\n(add_net \"T3_3\")\n )\n\n \n\n (module trace_test (layer F.Cu) (tedit 5CF31DEF)\n\n (at 1 -1 30)\n\n (pad 1 smd rect (at 0 0 30) (size 1 1) (layers F.Cu F.Paste F.Mask)\n (net 1 \"P1\") (solder_mask_margin 0.2))\n\n (pad 2 smd rect (at 5 5 30) (size 1 1) (layers F.Cu F.Paste F.Mask)\n (net 1 \"P1\") (solder_mask_margin 0.2))\n\n )\n\n (segment (start 1 -1) (end 7.830127 0.8301270000000001) (width 0.25) (layer F.Cu) (net 1))\n\n \n\n\n (module zone_test (layer F.Cu) (tedit 5CF31DEF)\n\n (at 1 -1 30)\n\n (pad 1 smd rect (at 0 0 30) (size 1 1) (layers F.Cu F.Paste F.Mask)\n (net 1 \"P1\") (solder_mask_margin 0.2))\n\n (pad 2 smd rect (at 5 5 30) (size 1 1) (layers F.Cu F.Paste F.Mask)\n (net 1 \"P1\") (solder_mask_margin 0.2))\n\n )\n\n (zone (net 1) (net_name P1) (layer F.Cu) (tstamp 0) (hatch full 0.508)\n (connect_pads (clearance 0.508))\n (min_thickness 0.254)\n (fill yes (arc_segments 32) (thermal_gap 0.508) (thermal_bridge_width 0.508))\n (polygon (pts (xy 7.830127 0.8301270000000001) (xy 2.830127 -7.830127) (xy -5.830127 -2.830127) (xy -0.8301270000000001 5.830127)))\n )\n\n \n \n\n (module dynamic_net_test (layer F.Cu) (tedit 5CF31DEF)\n\n (at 0 0 0)\n\n (pad 1 smd rect (at 0 0 0) (size 1 1) (layers F.Cu F.Paste F.Mask)\n (net 2 \"T3_1\") (solder_mask_margin 0.2))\n\n (pad 1 smd rect (at 0 0 0) (size 1 1) (layers F.Cu F.Paste F.Mask)\n (net 3 \"T3_2\") (solder_mask_margin 0.2))\n\n (pad 1 smd rect (at 0 0 0) (size 1 1) (layers F.Cu F.Paste F.Mask)\n (net 4 \"T3_3\") (solder_mask_margin 0.2))\n\n )\n\n \n \n\n (module anchor_test (layer F.Cu) (tedit 5CF31DEF)\n\n (at 0 0 0)\n\n (fp_line (start 0 0) (end 10 -10) (layer Dwgs.User) (width 0.05))\n\n )\n\n \n (gr_line (start -9.5 9.5) (end 9.5 9.5) (angle 90) (layer Edge.Cuts) (width 0.15))\n(gr_line (start 9.5 9.5) (end 9.5 -9.5) (angle 90) (layer Edge.Cuts) (width 0.15))\n(gr_line (start 9.5 -9.5) (end -9.5 -9.5) (angle 90) (layer Edge.Cuts) (width 0.15))\n(gr_line (start -9.5 -9.5) (end -9.5 9.5) (angle 90) (layer Edge.Cuts) (width 0.15))\n \n)\n\n " } \ No newline at end of file