From 3745cf3c47948113f5932e0ef1c56bd53f9282fe Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?B=C3=A1n=20D=C3=A9nes?= Date: Wed, 15 Dec 2021 21:42:37 +0100 Subject: [PATCH] Parameterize PCB component reference hiding --- src/pcbs.js | 11 ++++++----- test/helpers/mock_footprints.js | 8 ++++++++ ...{001_mock_footprints.yaml => mock_footprints.yaml} | 0 ...prints___pcbs.json => mock_footprints___pcbs.json} | 0 test/pcbs/references.yaml | 11 +++++++++++ test/pcbs/references___pcbs.json | 4 ++++ 6 files changed, 29 insertions(+), 5 deletions(-) rename test/pcbs/{001_mock_footprints.yaml => mock_footprints.yaml} (100%) rename test/pcbs/{001_mock_footprints___pcbs.json => mock_footprints___pcbs.json} (100%) create mode 100644 test/pcbs/references.yaml create mode 100644 test/pcbs/references___pcbs.json diff --git a/src/pcbs.js b/src/pcbs.js index 0fbf309..90c0a82 100644 --- a/src/pcbs.js +++ b/src/pcbs.js @@ -149,7 +149,7 @@ exports.inject_footprint = (name, fp) => { footprint_types[name] = fp } -const footprint = exports._footprint = (config, name, points, point, net_indexer, component_indexer, units) => { +const footprint = exports._footprint = (config, name, points, point, net_indexer, component_indexer, units, extra) => { if (config === false) return '' @@ -181,7 +181,7 @@ const footprint = exports._footprint = (config, name, points, point, net_indexer // reference const component_ref = parsed_params.ref = component_indexer(parsed_params.param.class || '_') - parsed_params.ref_hide = 'hide' // TODO: make this parametric? + parsed_params.ref_hide = extra.references ? '' : 'hide' // footprint positioning parsed_params.at = `(at ${anchor.x} ${-anchor.y} ${anchor.r})` @@ -240,7 +240,8 @@ exports.parse = (config, points, outlines, units) => { for (const [pcb_name, pcb_config] of Object.entries(pcbs)) { // config sanitization - a.unexpected(pcb_config, `pcbs.${pcb_name}`, ['outlines', 'footprints']) + a.unexpected(pcb_config, `pcbs.${pcb_name}`, ['outlines', 'footprints', 'references']) + const references = a.sane(pcb_config.references || false, `pcbs.${pcb_name}.references`, 'boolean')() // outline conversion if (a.type(pcb_config.outlines)() == 'array') { @@ -276,7 +277,7 @@ exports.parse = (config, points, outlines, units) => { // key-level footprints for (const [p_name, point] of Object.entries(points)) { for (const [f_name, f] of Object.entries(point.meta.footprints || {})) { - footprints.push(footprint(f, `${p_name}.footprints.${f_name}`, points, point, net_indexer, component_indexer, units)) + footprints.push(footprint(f, `${p_name}.footprints.${f_name}`, points, point, net_indexer, component_indexer, units, {references})) } } @@ -286,7 +287,7 @@ exports.parse = (config, points, outlines, units) => { } const global_footprints = a.sane(pcb_config.footprints || {}, `pcbs.${pcb_name}.footprints`, 'object')() for (const [gf_name, gf] of Object.entries(global_footprints)) { - footprints.push(footprint(gf, `pcbs.${pcb_name}.footprints.${gf_name}`, points, undefined, net_indexer, component_indexer, units)) + footprints.push(footprint(gf, `pcbs.${pcb_name}.footprints.${gf_name}`, points, undefined, net_indexer, component_indexer, units, {references})) } // finalizing nets diff --git a/test/helpers/mock_footprints.js b/test/helpers/mock_footprints.js index c822eb1..80bea95 100644 --- a/test/helpers/mock_footprints.js +++ b/test/helpers/mock_footprints.js @@ -113,4 +113,12 @@ exports.inject = (ergogen) => { ` } }) + + ergogen.inject_footprint('references_test', { + nets: {}, + params: {}, + body: p => { + return `references ${p.ref_hide ? 'hidden' : 'shown'}` + } + }) } \ No newline at end of file diff --git a/test/pcbs/001_mock_footprints.yaml b/test/pcbs/mock_footprints.yaml similarity index 100% rename from test/pcbs/001_mock_footprints.yaml rename to test/pcbs/mock_footprints.yaml diff --git a/test/pcbs/001_mock_footprints___pcbs.json b/test/pcbs/mock_footprints___pcbs.json similarity index 100% rename from test/pcbs/001_mock_footprints___pcbs.json rename to test/pcbs/mock_footprints___pcbs.json diff --git a/test/pcbs/references.yaml b/test/pcbs/references.yaml new file mode 100644 index 0000000..1947118 --- /dev/null +++ b/test/pcbs/references.yaml @@ -0,0 +1,11 @@ +points.zones.matrix: + columns.one: + rows.only: +pcbs: + shown: + references: true + footprints: + - type: references_test + hidden: + footprints: + - type: references_test \ No newline at end of file diff --git a/test/pcbs/references___pcbs.json b/test/pcbs/references___pcbs.json new file mode 100644 index 0000000..0a24f58 --- /dev/null +++ b/test/pcbs/references___pcbs.json @@ -0,0 +1,4 @@ +{ + "shown": "\n \n(kicad_pcb (version 20171130) (host pcbnew 5.1.6)\n\n (page A3)\n (title_block\n (title shown)\n (rev v1.0.0)\n (company Unknown)\n )\n\n (general\n (thickness 1.6)\n )\n\n (layers\n (0 F.Cu signal)\n (31 B.Cu signal)\n (32 B.Adhes user)\n (33 F.Adhes user)\n (34 B.Paste user)\n (35 F.Paste user)\n (36 B.SilkS user)\n (37 F.SilkS user)\n (38 B.Mask user)\n (39 F.Mask user)\n (40 Dwgs.User user)\n (41 Cmts.User user)\n (42 Eco1.User user)\n (43 Eco2.User user)\n (44 Edge.Cuts user)\n (45 Margin user)\n (46 B.CrtYd user)\n (47 F.CrtYd user)\n (48 B.Fab user)\n (49 F.Fab user)\n )\n\n (setup\n (last_trace_width 0.25)\n (trace_clearance 0.2)\n (zone_clearance 0.508)\n (zone_45_only no)\n (trace_min 0.2)\n (via_size 0.8)\n (via_drill 0.4)\n (via_min_size 0.4)\n (via_min_drill 0.3)\n (uvia_size 0.3)\n (uvia_drill 0.1)\n (uvias_allowed no)\n (uvia_min_size 0.2)\n (uvia_min_drill 0.1)\n (edge_width 0.05)\n (segment_width 0.2)\n (pcb_text_width 0.3)\n (pcb_text_size 1.5 1.5)\n (mod_edge_width 0.12)\n (mod_text_size 1 1)\n (mod_text_width 0.15)\n (pad_size 1.524 1.524)\n (pad_drill 0.762)\n (pad_to_mask_clearance 0.05)\n (aux_axis_origin 0 0)\n (visible_elements FFFFFF7F)\n (pcbplotparams\n (layerselection 0x010fc_ffffffff)\n (usegerberextensions false)\n (usegerberattributes true)\n (usegerberadvancedattributes true)\n (creategerberjobfile true)\n (excludeedgelayer true)\n (linewidth 0.100000)\n (plotframeref false)\n (viasonmask false)\n (mode 1)\n (useauxorigin false)\n (hpglpennumber 1)\n (hpglpenspeed 20)\n (hpglpendiameter 15.000000)\n (psnegative false)\n (psa4output false)\n (plotreference true)\n (plotvalue true)\n (plotinvisibletext false)\n (padsonsilk false)\n (subtractmaskfromsilk false)\n (outputformat 1)\n (mirror false)\n (drillshape 1)\n (scaleselection 1)\n (outputdirectory \"\"))\n )\n\n (net 0 \"\")\n \n (net_class Default \"This is the default net class.\"\n (clearance 0.2)\n (trace_width 0.25)\n (via_dia 0.8)\n (via_drill 0.4)\n (uvia_dia 0.3)\n (uvia_drill 0.1)\n (add_net \"\")\n )\n\n references shown\n \n \n)\n\n ", + "hidden": "\n \n(kicad_pcb (version 20171130) (host pcbnew 5.1.6)\n\n (page A3)\n (title_block\n (title hidden)\n (rev v1.0.0)\n (company Unknown)\n )\n\n (general\n (thickness 1.6)\n )\n\n (layers\n (0 F.Cu signal)\n (31 B.Cu signal)\n (32 B.Adhes user)\n (33 F.Adhes user)\n (34 B.Paste user)\n (35 F.Paste user)\n (36 B.SilkS user)\n (37 F.SilkS user)\n (38 B.Mask user)\n (39 F.Mask user)\n (40 Dwgs.User user)\n (41 Cmts.User user)\n (42 Eco1.User user)\n (43 Eco2.User user)\n (44 Edge.Cuts user)\n (45 Margin user)\n (46 B.CrtYd user)\n (47 F.CrtYd user)\n (48 B.Fab user)\n (49 F.Fab user)\n )\n\n (setup\n (last_trace_width 0.25)\n (trace_clearance 0.2)\n (zone_clearance 0.508)\n (zone_45_only no)\n (trace_min 0.2)\n (via_size 0.8)\n (via_drill 0.4)\n (via_min_size 0.4)\n (via_min_drill 0.3)\n (uvia_size 0.3)\n (uvia_drill 0.1)\n (uvias_allowed no)\n (uvia_min_size 0.2)\n (uvia_min_drill 0.1)\n (edge_width 0.05)\n (segment_width 0.2)\n (pcb_text_width 0.3)\n (pcb_text_size 1.5 1.5)\n (mod_edge_width 0.12)\n (mod_text_size 1 1)\n (mod_text_width 0.15)\n (pad_size 1.524 1.524)\n (pad_drill 0.762)\n (pad_to_mask_clearance 0.05)\n (aux_axis_origin 0 0)\n (visible_elements FFFFFF7F)\n (pcbplotparams\n (layerselection 0x010fc_ffffffff)\n (usegerberextensions false)\n (usegerberattributes true)\n (usegerberadvancedattributes true)\n (creategerberjobfile true)\n (excludeedgelayer true)\n (linewidth 0.100000)\n (plotframeref false)\n (viasonmask false)\n (mode 1)\n (useauxorigin false)\n (hpglpennumber 1)\n (hpglpenspeed 20)\n (hpglpendiameter 15.000000)\n (psnegative false)\n (psa4output false)\n (plotreference true)\n (plotvalue true)\n (plotinvisibletext false)\n (padsonsilk false)\n (subtractmaskfromsilk false)\n (outputformat 1)\n (mirror false)\n (drillshape 1)\n (scaleselection 1)\n (outputdirectory \"\"))\n )\n\n (net 0 \"\")\n \n (net_class Default \"This is the default net class.\"\n (clearance 0.2)\n (trace_width 0.25)\n (via_dia 0.8)\n (via_drill 0.4)\n (uvia_dia 0.3)\n (uvia_drill 0.1)\n (add_net \"\")\n )\n\n references hidden\n \n \n)\n\n " +}