PCB layout done
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852ebbcf95
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11 changed files with 234 additions and 46 deletions
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@ -7,14 +7,14 @@ module.exports = {
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${p.at /* parametric position */}
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${''/* corner marks */}
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(fp_line (start -7 -6) (end -7 -7) (layer F.SilkS) (width 0.15))
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(fp_line (start -7 7) (end -6 7) (layer F.SilkS) (width 0.15))
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(fp_line (start -6 -7) (end -7 -7) (layer F.SilkS) (width 0.15))
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(fp_line (start -7 7) (end -7 6) (layer F.SilkS) (width 0.15))
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(fp_line (start 7 6) (end 7 7) (layer F.SilkS) (width 0.15))
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(fp_line (start 7 -7) (end 6 -7) (layer F.SilkS) (width 0.15))
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(fp_line (start 6 7) (end 7 7) (layer F.SilkS) (width 0.15))
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(fp_line (start 7 -7) (end 7 -6) (layer F.SilkS) (width 0.15))
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(fp_line (start -7 -6) (end -7 -7) (layer Dwgs.User) (width 0.15))
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(fp_line (start -7 7) (end -6 7) (layer Dwgs.User) (width 0.15))
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(fp_line (start -6 -7) (end -7 -7) (layer Dwgs.User) (width 0.15))
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(fp_line (start -7 7) (end -7 6) (layer Dwgs.User) (width 0.15))
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(fp_line (start 7 6) (end 7 7) (layer Dwgs.User) (width 0.15))
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(fp_line (start 7 -7) (end 6 -7) (layer Dwgs.User) (width 0.15))
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(fp_line (start 6 7) (end 7 7) (layer Dwgs.User) (width 0.15))
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(fp_line (start 7 -7) (end 7 -6) (layer Dwgs.User) (width 0.15))
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${''/* pins */}
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(pad 1 thru_hole circle (at 2.5 -4.5) (size 2.25 2.25) (drill 1.47) (layers *.Cu *.Mask) ${p.net_from})
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